1、8x100G Solution for SR Scenario
a) 800G SR scenario requirement analysis
For the class of 100m, the industry is facing the basic limitations of VCSEL signaling at speeds of 100G/lane. Here, multi-mode technology will likely allow for reaches of 30-50m, thus only partially covering the SR class, which is primarily employed by Chinese hyper scale data center operators. The 800G MSA targets the development of a low-cost 8x100G module for SR applications, covering the sweet spot of 60-100m, as shown in Figure 1. Particularly, the 800G MSA is intended to specify a lower cost transmitter technology with the potential to leverage sub-linear cost scaling with a high degree of integration. Such a module would allow for an early time-to-market dense 800G solution. A low cost 800G SR8 could also support the potential trends of an increasing switch radix and decreasing server count-per-rack. As shown in Figure 1, the 800G MSA will define a lower cost PMD for single mode fiber interconnects based on 100G PAM4. Due to the low latency requirements of SR applications, KP4 forward error correction (FEC) will be used end-to-end with a simple clock recovery and data equalization unit in the module. Finally, the 800G MSA will specify a connector for the PSM8 modules which enables a fan-out to 8x100G.
It seems that compared to the conventional SR module, the 800G SR8 will no longer adopt a VCSEL based multi-mode solution, but will adopt a parallel single-mode transmission method, namely PSM8, with a modulation format of PAM4 contains a DSP chip.
b) Technical Feasibility of 8x100G solutions
As mentioned above, signaling rate up to 100G per lane may limit the evolvement of multi-mode fiber (MMF) based solution from 400G-SR8 to 800G-SR8. Based on the theoretical model used in IEEE, we can reckon that the transmission distance that MMF can support is no more than 50m as the baud rate up to 50G (See Table 1). The limitation factors are from the limited bandwidth of VCSEL and the modal dispersion of MMF. With the optimization in devices, fiber medium as well as enhanced DSP algorithms, 100m MMF transmission may be realized at the cost of higher expense, higher latency, and larger power consumption. Hence, in 800G Pluggable MSA, we recommend that the 800G-SR8 scenario is taken over by SMF based solution.
In order to guarantee the advantages on the cost and power consumption of the SMF based solution, reasonable PMD standard requirements are indispensable in 800G-SR8. The PMD requirements to be defined should ensure that
1) diverse transmitter techniques, such as DML, EML, and silicon photonics (SiPh), can be applied in such scenario;
2) all the potential of the components can be released adequately to achieve the targeting link performance;
3) key parameters in PMD layers should be relaxed as much as possible, in the context of maintaining a reliable link performance. According to these three principles, we will conduct some brief investigations and discussions as follows.
The power budget of the SMF based 800G-SR8 solution would be quite similar with that defined in IEEE 400G-SR8. The only issue to be determined is the insertion loss of new defined PSM8 SMF connectors. It means that the power budget in SR scenario can be achieved without a hitch based on currently mature optical and electronic components and DSP ASICs used in 400GE optical interconnection. Therefore, apart from specifying the connector for the PSM8 modules, the key issue for the definition of PMD parameters in 800 SR8 scenario is to find out the suitable optical modulation amplitude (OMA), extinction ratio (ER), transmitter dispersion eye closure quaternary (TDECQ) of the transmitter and sensitivity of receiver. In order to set these parameters into the suitable position, the bit error ration (BER) performance of the diverse transmitters is investigated and assessed, as shown in Figure 2.
2、4x200G Solution for FR Scenario
a)800G FR scenario requirement analysis
200G per lane PAM4 technology is the next major technological step for optical intensity modulated, direct detection interconnects and will be the foundation for a 4-lane 800G connectivity, as well as an essential building block for future 1.6Tb/ s interconnects. As shown in Figure 3, the MSA will define the full PMD and partial PMA layers including a new low power, low latency FEC as a wrapper on top of the KP4 FEC of the 112G electrical input signals, in order to improve the net coding gain (NCG) of the modem. One of the key goals of this industry alliance will be the development of new wide bandwidth electrical and optical analog components for the transmitter and receiver assemblies including digital-to-analog and analog-to-digital (AD/ DA) converters. In order to achieve the aggressive power envelop targets of pluggable modules, the DSP chips will be designed in CMOS process with lower nm node and employ low power signal processing algorithms to achieve equalization of the channel.
b) Technical feasibility of 4x200G solution
Considering that a temperature controller (TEC) is required in LAN-WDM, which is not desired in 200G/lane scenarios, the power budget will be analyzed based on CWDM4. Link insertion loss, multipath interference (MPI), differential group delay (DGD), and transmitter dispersion penalty (TDP) are the contributions to the link power budget. According to the model released in IEEE standards, MPI and DGD penalty is calculated as listed in Table 2. In view of the increased baud rate of 200G per lane, the dispersion penalty is expected to be larger than that in 100G per lane. A reasonable suggestion for transmitter dispersion penalty (TDP) is 3.9 dB. Hence, taking into account the margin for receiver aging and coupling loss, as well as the typical launching optical power value of the transmitter, we think the receiver sensitivity required should be around -5dBm.
Link performance of 200G/pane is presented using simulation and experiment. The parameters of the devices adopted in the link are listed in Table 3. The experimental result shows that the receiver sensitivity can reach the target value while the new FEC’s threshold is set to 2E-3 as depicted in Figure 4 (a). However, in this experiment, maximum likelihood sequence estimation (MLSE) was required to compensate the excessive inter-symbol-interference induced by channel bandwidth limitation. The dash line in Figure 4 (a) shows the simulation based on the model in which the measured parameters of the devices used in the experiment are adopted. Together with experimental results, simulations show that the system is limited by the bandwidth of components, such as AD/DA, driver and E/O modulators. Considering that high bandwidth components are expected to be available in the years to come, simulation results by using the same system model but with expanded bandwidth is illustrated in Figure 4 (b). It shows the receiver sensitivity of Pre FEC BER=2e-3 can meet the above-mentioned requirement with only FFE equalization in the DSP unit, which is in accordance with the theoretical expectation.
Based on the above analysis, TDECQ is still suggested to be followed in compliance testing in the 800G-FR4 scenario. However, FFE tap numbers of the reference receiver adopted in TDECQ measurement is anticipated to be increased to a reasonable value and needs to be further discussed. Additionally, it should be noted that if the ability of future device targeting 100Gbaud underperforms our expectation, more complicated algorithms (e.g. MLSE) may be used in FR4 scenarios, which implies that a new compliance metrology must be developed.
c)Packaging for 4x200G solution
For the 4x200G module, the packaging for both the transmitter and receiver needs to be reconsidered to ensure signal integrity within the range under the Nyquist frequency point (56GHz). Two possible solutions for the transmitter are illustrated in Figure 5. Solution A is a traditional approach where the modulator driver (DRV) is close to the modulator. In contrast, in Solution B, DRV in flip-chip design is co-packaged with the DSP unit to optimize the signal integrity on the RF transmission line. Both of these two solutions can be realized by the state-of-art technology. Preliminary simulations show that Solution B can achieve good results and can ensure a bandwidth larger than 56GHz. The ripples on the S21 curve of Solution A are due to the reflection on DRV input and can be optimized through the matching design of the DRV. Eventually, it is expected that the overall performance of Solution A can be further improved.
3.Possible solutions for 800G DR scenario
As shown in Table 3, there are four possible routes in 800 DR scenario. First, 800G SR8 solutions defined in 800G MSA could be defined to extend the reach to 500m. Since parallel fiber solutions require more lanes of fiber, the fiber cost up to 500m is the main concern in this scenario. Second, the 2x400G CWDM4 solution utilizes the available FR4 solution with doubling the pairs of transmitters and receivers. This solution seems to be the balance between fiber resource and technical maturity. However, the power consumption and module cost are its main limitations. Third, there is a possibility that next generation 200G/lane solution may cover this scenario. This solution is believed to be the lowest cost and power consumption with only 4 pairs of transmitter and receivers. As for the available time of this solution, it still requires the feasibility demonstration and industrial maturity considerations.
In summary, several solutions are discussed for the DR use case. The MSA will keep track on the technical development, and give suggestions on this application in future.
4.Summary and Outlook
In summary, two scenarios, i.e. 800G-SR8 and 800G-FR4, will be defined first in the 800G Pluggable MSA. In the SR8 scenario, to accommodate more technologies into consideration and thus obtain a competitive SMF-based solution, we consider to adjust some key parameters in PMD layer. Therefore, OMA and ER would be relaxed for power consumption, and the reference receiver used in TDECQ measurement would be redefined. We also demonstrated the technical feasibility of 200G/lane optical transmission for 800G-FR4 applications. The experiments and simulations show that a low power, low latency FEC sub-layer should be added into the optical module to achieve the targeting power budget. The details of this new FEC will be presented in the 800G-FR4 standard specifications as so to guarantee the interoperability. Meanwhile, the bandwidth improvement of the components and packaging design optimization are the other two issues that yet require thorough investigations.
The 800G Pluggable MSA targets to release first specifications in Q4/2020, with several subcomponents targeted in the MSA already being prototyped and first 800G modules expected to sample in 2021. With the 400GbE generation ready to be rolled out in the market, 800G pluggable modules will leverage this new eco-system and offer higher density and cost-optimized 100G/lane and 200G/lane interconnects for the next generation of 25.6T and 51.2T switches.
Looking beyond 800G towards 1.6T, the industry begins to see the possible limitations of pluggable modules. SerDes for C2M interconnects is unlikely to scale to 200G/lane using classical PCBs, which might require bringing analog electronics and optics closer to the switching ASIC. But whether the path is leading to co-packaged optics, on-board optics or an evolution of pluggables, we believe that 200G/lane interconnects defined in this MSA, will be an essential building block of the 800G and 1.6T interconnect generations.